Hardware Digital Sliding Average Filter

Abstract

The implementation of streaming filtering of digital signals requires calculating the convolution of the signal with the impulse response of the filter in real time. This implies the use of digital signal processors or field programmable gate array. Let's assume that the signals are received from various sensors by passing through an analog-to-digital converter. As a rule, these are low-frequency signals with additive Gaussian noise, the sampling frequency of which is less than 200 kHz. Their filtering does not impose high requirements for the computing system (in terms of performance and/or a large number of processing channels). For this reason, universal high-performance systems turn out to be inefficient and excessive in terms of cost, complexity of development and power consumption. Therefore, the filter is implemented on simple and cheap models of microcontrollers, which is designed to solve control problems (not for intensive calculation). As a result, the solution turns out to be inefficient in terms of the clock cycles spent on each sample of the signal. Sliding averaging filters of a small order (up to 16) are well suited for streaming digital processing signals from sensors that continuously measure physical quantities. Due to this, a hardware multiplier and a large amount of memory are not required. To implement such filters, it is proposed to develop a simple and cheap hardware that can solve the problem effectively. Based on typical discrete elements, the hardware implementation of a sliding averaging filter is considered. In conclusion, the result is extrapolated to the integrated technology. The signal processing speed is expected to exceed several million samples per second.