Evaluating the Reliability Testing Acceleration Factor Based on VLSI Chip Infrared Image Analysis

Abstract

A new approach for evaluating the acceleration factor of forced reliability tests of very large scale integrated circuits (VLSI) is presented. The approach is based on subjecting the VLSI chip to an infrared image analysis. Currently, the VLSI reliability testing acceleration factor is evaluated based on the Arrhenius law, according to which this factor depends on the chip temperature. The chip temperature, in turn, is represented by the sum of the chip package temperature and the product of the maximum dissipated power and the chip-to-package thermal resistance. The drawback of the existing method is that the calculation is carried out for only a single chip temperature value that was obtained analytically. But the VLSI is a complex system, and it is not correct to judge about the testing acceleration factor proceeding from a single chip temperature value. It is proposed to calculate the VLSI reliability testing acceleration factor based on the temperatures at many points on the VLSI chip surface. This will make it possible to take into account the test sequence influence on the temperature distribution over the chip surface, thereby helping select the test sequences so that to obtain the maximal and uniform chip heating. Owing to the proposed method, it becomes possible to evaluate the testing acceleration factor more accurately and also to potentially increase it by choosing the test sequence. A more accurate evaluation of the acceleration factor allows the reliability tests reliability to be improved. The proposed method for evaluating the acceleration factor was validated experimentally. The workplace is described, the calculations of the reliability testing acceleration factors using two approaches are carried out, and their comparison is given.